1. Field of the Invention
The present invention generally relates to a method and apparatus for retaining a workpiece within a semiconductor wafer processing system, and more particularly, to a method and apparatus for minimizing plasma destabilization while chucking or dechucking a wafer from an electrostatic chuck within a semiconductor wafer processing system.
2. Description of the Background Art
Electrostatic chucks are used for retaining a workpiece, such as a semiconductor wafer, upon a pedestal within a semiconductor wafer processing system such that the wafer can be processed. Although electrostatic chucks vary in design, they are all based upon the principle of applying a fixed voltage to one or more electrodes embedded in the chuck to establish an electric field between the chuck and the wafer. The electric field induces opposite polarity charges to accumulate on the wafer and the electrodes, respectively. The electrostatic attractive force between the oppositely polarized charges pulls the wafer toward the chuck, thereby retaining the wafer upon the chuck. In a Coulombic type chuck, the magnitude of the retention force is directly proportional to the potential difference between the wafer and the chuck electrodes. In a Johnsen-Rahbek type chuck, where the chuck material has a finite resistivity and charges migrate from the electrodes to the chuck surface, the magnitude of the retention force is directly proportional to the square of the potential difference between the wafer and the chuck surface.
The chucking voltage that provides the best process results is empirically determined by processing a number of "dummy" wafers at a variety of chucking voltages. The chucking voltage that produces the best results is then repeatedly used to process wafers. During processing, each wafer is retained using the same fixed chucking voltage. Variations in the process parameters that may effect chucking force, chuck leakage current, backside gas cooling efficiency and the like are not taken into account while processing a wafer. As such, one chucking voltage is used to fit all chucking situations. As shall be discussed next, this chucking voltage can lead to processing anomalies, intermittent wafer sticking or substantial helium leaking.
In semiconductor wafer processing equipment, an electrostatic chuck forms a portion of a pedestal assembly. The pedestal assembly contains various components for heating or cooling the wafer, providing wafer bias, providing plasma power (cathode electrode) and routing power to the electrostatic chuck. The electrostatic chuck is used for clamping wafers to the pedestal during processing. Since the materials and processes used to process a wafer are extremely temperature sensitive, temperature control is an important aspect of wafer processing. Should the wafer material be exposed to excessive temperature fluctuations resulting from poor heat transfer during processing, performance of the wafer process may be compromised resulting in wafer damage. As such, the pedestal generally forms a heat sink or heat source as used in etching, physical vapor deposition (PVD) or chemical vapor deposition (CVD) applications. To optimally transfer heat between the wafer and pedestal, a very nearly uniform electrostatic force should be used in an attempt to cause the greatest amount of wafer surface to physically contact a support surface of the chuck and contact the surface with a uniform force.
During wafer processing, while the chucking voltage is substantially constant, the chucking force retaining a wafer varies considerably during a given process sequence or recipe. Generally, a nominal, fixed chucking voltage is applied to the chucking electrodes to provide a large nominal retention force that, as the chamber environment varies, the wafer will remain relatively stationary. Although the wafer is stationary, the heat transfer characteristics vary considerably. For example, as a process recipe is performed, the RF input power and chamber pressure are varied. If the voltage applied to the chucking electrode is fixed, such variations in chamber environment will cause the force retaining the wafer to fluctuate due to changing DC bias. Variability in the chucking force produces variations in the contact area between the chuck and wafer resulting in variations in the heat transfer from the wafer to the chuck as well as variations in the backside gas (e.g., helium) leak rate from beneath the wafer.
Also, chucking force variations as a wafer is being processed can cause friction between the wafer and the chuck surface that generates particulate contaminants that contaminate the backside of the wafer. Additionally, excessive chucking force can increase the time required to release the wafer after the process is complete (dechucking time). In order to minimize the dechucking time, thereby maximize throughput, it is desirable to apply the minimum chucking force required to achieve good heat transfer. To achieve maximum throughput of wafers that are all uniformly processed, it is also desirable to ensure that the chucking force used from wafer to wafer is uniform as different wafers are processed.
Wafer dechucking is generally accomplished by applying an oppositely polarized voltage compared to the chucking voltage or a similarly polarized voltage at a lesser magnitude as the chucking voltage to remove residual charges from the wafer and chuck. Such dechucking methods are well known in the art and, for example, are described in commonly assigned U.S. Pat. No. 5,459,632 issued to Birang et al. on Oct. 17, 1995. The methods used to dechuck a wafer generally apply a fixed dechucking voltage that is proportional to the magnitude of the chucking voltage. The same chucking and dechucking voltages are used for oxide wafers as well as silicon wafers or any other type of wafer. Such uniform chucking and dechucking voltages can result in wafer "sticking" after a dechucking voltage has been applied. Such sticking is especially problematic in Johnsen-Rahbek type chucks.
As mentioned above, in a Johnsen-Rahbek type chuck, the chuck body is fabricated from a finite resistivity material, e.g., doped aluminum nitride, that enables charges to migrate from the chuck electrodes to the surface of the chuck. Consequently, a small current flows through the wafer at contact points between the chuck surface and the wafer. This current flow, as expected, varies with the resistance of the wafer backside contact points to the chuck surface. As such, an oxide wafer, having a high resistivity surface, conducts very little current. While a silicon wafer, having a low resistivity surface, conducts a substantial current. If a single chucking voltage is used for all forms of wafers, some wafers (e.g., silicon wafers having a higher conductivity) would be chucked with a different force than other wafers (e.g., oxide wafers having a lower conductivity). An increase in chucking force increases the contact area between the wafer and chuck surface and results in increased leakage current flow, and vice versa for decreased chucking force. If an excessive leakage current flows through a wafer, the wafer can experience a charge imbalance that is not easily removed from the chuck surface. Such an imbalance results in a residual charge remaining on the wafer after a dechucking voltage has been applied. This residual charge is the cause of wafer "sticking". However, since various wafer types can handle various amounts of leakage current, merely limiting the chucking voltage to a value that ensures a "safe" leakage current in all wafer types results in various types of wafers being chucked with widely varying chucking forces.
As such, some wafers may be inadequately chucked and other wafers may be excessively chucked.
The leakage current for an oxide wafer is thousands of times higher for Johnsen-Rahbek chucks than for polyimide chucks. Johnsen-Rahbek chucks have a leakage current of tens to hundreds of microamps, whereas polyimide chucks have a leakage current in the nanoamp range. If the electrode current I.sub.elec is defined as the total flow of positive charge to the electrode per unit time, the electrode current can be represented as EQU I.sub.elec =.DELTA.V/R.sub.leak +Cd(.DELTA.V)/dt+I.sub.emis (1)
where .DELTA.V is defined as the voltage difference between the electrode voltage V.sub.e and the wafer self bias voltage V.sub.dc, .DELTA.V.ident.V.sub.e -V.sub.dc, R.sub.leak represents the equivalent resistance between the electrode and wafer, C represents the electrode to wafer capacitance, and I.sub.emis represents the component of current caused by electron emission from the surface of the wafer or chuck and becomes significant only under conditions of high .vertline..DELTA.V.vertline.. The total leakage current thus has a steady-state component that depends on the resistivity of the chuck and on contact resistance, which is highly wafer type dependent, and a transient component due to changes in .DELTA.V over time. In practice, the electrode current appears as a positive surge up to about 1 mA during RF ramp up (because V.sub.e is increasing and V.sub.dc is decreasing as RF power increases), a steady or slowly increasing current of about 60 .mu.A during plasma on, and a negative surge down to -1 mA during RF ramp down (because V.sub.e is decreasing and V.sub.dc is increasing as RF power decreases).
The chucking force is proportional to (.DELTA.V/d).sup.2, where d represents an effective distance between the wafer and surface of the chuck. As such, it is possible to chuck the wafer with a positive or negative .DELTA.V. However, standard state-of-the-art wafer processing systems use a V.sub.e that results in a positive .DELTA.V. These standard designs in effect leverage V.sub.dc, which is negative hundreds of Volts, to produce a larger chucking force for a given magnitude V.sub.e than if .DELTA.V were negative. Lower voltages are thus applied to critical components inside the high voltage power supply and on critical electrostatic chuck and cathode components, generally lowering the risk of arcing. Heretofore, there has been no known benefit in designing wafer processing systems with a negative .DELTA.V.
By closely examining the transient behavior of the electrode current by monitoring the current from the high voltage supply and visually observing the plasma behavior, it has been found that a positive electrode current destabilizes the plasma in capacitively coupled discharge chambers. This plasma destabilization is seen as small sparks around the chamber liner and end point window and concomitantly as positive current spikes with a fast rise-time (&lt;100 .mu.s) and an exponential-like fall-time of several milliseconds. The current spikes vary in frequency and size with wafer type and with the magnitude of the average DC current injected into the electrode (which of course flows into the plasma). These current spikes are 10-200 .mu.A in amplitude, a value which tends to be comparable to the average positive DC current. At average current levels in the 10 .mu.A range, the spikes tend to be 1-5 .mu.A in size and appear randomly in time every 0.1 s to 1 s. When the average DC current is increased to 100 .mu.A, the current spikes tend to be 20-50 .mu.A in magnitude and appear randomly every 5-2 ms. Their size is larger when there is a longer time between spikes. The current spikes have been correlated with presence of aluminum oxide particles on the wafer and may also cause plasma-induced device damage. The presence of current spikes also has been correlated with loss of chucking force.
The appearance of the current spikes and concomitant plasma destabilization is due to a gradual increase in average plasma potential and V.sub.dc over time with respect to ground (the conductive chamber body) as electrons are removed from the plasma by the driving of positive current to the electrode. As electrons are removed, ions are ejected from the plasma to the walls to maintain quasineutrality of the bulk plasma. If the chamber walls have a nonconductive layer (e.g., anodized and polymer coated chamber walls) between the plasma and the conductive part of the chamber wall, electrons on the interior surface of this layer facing the plasma recombine with the ions, producing a deficiency of electrons on this surface, which in turn produces a voltage drop across this nonconductive layer. Then when this potential drop exceeds a particular value of perhaps 100-200V across this layer, electrons at the conductive wall on the other side of the nonconductive layer may break through at a weak localized area in the nonconductive layer. This localized area may heat, or arc, cause a localized plasma nonuniformity, and cause electrons at this location to stream into the plasma, producing equilibrium in the plasma once again. The cycle then repeats. Clearly, this is undesirable because of particle contamination and plasma nonuniformity-induced damage.
Therefore, it is desirable to determine optimal chucking parameters for a wafer to minimize plasma destabilization.